CN9130 SOM Hardware User Manual

Revision and Notes

Introduction

This document is intended for hardware engineers that are willing to integrate the CN9130 SOM from SolidRun ltd, into their own design.

The document provides details with regards CN9130 SOM rev 1.1.

The CN9130 SOM is pin and size compatible to the A388 SOM by SolidRun and can be used as an upgrade for the existing ClearFog Base and ClearFog Pro. 

Overview

CN9130 System On Module is a highly integrated SOM module based on Marvell’s CN9130 SoC.

The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 6 high speed SERDESs.

The module integrates the following features –

1. CN9130 SoC (up to 2.2GHz).

2.  On board 64bit DDR4 bus supporting up to 16GB at 2400MT/s without ECC

3. Single 12V or 5V DC-input is required.

Block Diagram

Open

CN9130 SOM Block Diagram

Specifications

Compatibility between SOMs A388 and CN9130  

Both SOMs have exactly the same form factor and footprint

The CN9130 SOM was designed to support SolidRun’s ClearFog Base/Pro. In case of any custom design based on A388 that wants to upgrade to CN9130, any case needs to be examined individually and  review carefully the borad-to-board pinout 

In the documentation section there is an excel table with exact pinout difference 

Main differences due to SoC pinout:

Power Consumption

The following power consumption measurements were conducted on the following setup:

1. Clearfog Pro carrier board

2. Voltage / current measurement on v_5v0 voltage rail

3. No mPCIe / USB / SATA / ETH cable were connected to the carrier board

4. Temperature measurement was taken from linux using the following command
   ‘cat /sys/class/thermal/thermal_zone?/temp’

5. Current and Voltage measured using an oscilloscope 

6. Linux command ‘memtester 100M > /dev/null &’ ran 4 times according to core count

7. Linux command ‘cpuburn-krait’ is ran 4 times in background. The reason cpuburn-krait was chosen is since it can generate most heat out of the cores (the core pipeline are most utilized)
    

Frequency Scaling

In order to improve power efficiency and increase temperature limits, SolidRun had enabled cpu frequency scaling.

Please refer to the patch below for more information.

Add linux patch - Enable the cpu frequency scaling · SolidRun/cn913x_build@5fe7734

SolidRun, recommends to not disable the frequency scaling feature.

Power Measurments

The measurements below were conducted without frequency scaling, to reflect the maximum power consumption:

CN9130 SOM extensions 

The CN9130 has two extension busses of  high performance, low latency and low power Marvell® MoChi interfaces (MCi). Each bus is comprised of 4x high speed differential pairs and a dedicated LVDS clock. Both busses are exposed through the SOM connector,  enabling to connect 1 or 2 additional 88F8215 comprising the kits of CN9131 and CN9132 on the carrier board and extending the SERDES count from 6 to 12 or 18. 

SERDES Muxing CN9130 – CP0:

The following port configuration can’t be used simultaneously:

• SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE

• SGMII port 1 and HS SGMII port 1

• SGMII port 2 and HS SGMII port 2

CORE Clock BOOT Straps

• PLL_SEL[0] – MPP[15] – CP_SPI1_MOSI

• PLL_SEL[1] – MPP[16] – CP_SPI1_SCK

• PLL_SEL[2] – MPP[17] – CP0_SYS_PLL_SEL2

• PLL_SEL[3] – MPP[46] (not exposed on B2B connector, 10K pull-down on SoM)

BOOT MODE BOOT Straps

• BOOT_MODE[0] – MPP18, 10K PU

• BOOT_MODE[1] – MPP19, 10K PU

• BOOT_MODE[2] – MPP20, 10K PD (not exposed on B2B connector)

• BOOT_MODE[3] – MPP21, 10K PU

• BOOT_MODE[4] – MPP22, 10K PU (not exposed on B2B connector)

• BOOT_MODE[5] – MPP23, 10K PU (not exposed on B2B connector)

CP0 MPP[62:0]