RZ/V2N SOM Hardware User Manual

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Revisions and Notes 

Introduction

This User Manual relates to the SolidRun’s RZV2N series, which includes.

• RZV2N Quad core ARM A55 (1.8GHz)

• RZV2NP Quad core ARM A55 (1.8GHz) w ISP

Overview

SolidRun’s RZV2N family is a high-performance 64-Bit Renesas. RZV2N Based SOMs with Integrated GPU for Next-Gen Human-Machine Interfaces, AI accelerator and ISP.

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZV2N SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support.

Highlighted Features

• Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).

• Renesas’s SoC supports QUAD version.

  • Quad Cortex A55 and up to 1.8GHz

  • Cortex-M33 subsystem processor supports real time tasks.

  • Encoder/Decoder (H.264/265).

  • AI accelerator; DRP-AI

  • ISP Mali-C55 (Optional)

  • Two CSI-2 (2 x 4 Lanes) and single DSI (4 Lanes)

  • High security engines.

  • Dual Ethernet interfaces.

  • PCIe Gen3 – two lanes

  • USB3.2 (Gen2, Host)

  • USB2.0 (Host/Device)

  • Up to six CAN interfaces.

• LPDDR4x memory in x32 configurations supports up to 8GB and up to 12.8GB/s. Supports in line ECC (16 ECC regions).

• Up to 128GB eMMC.

• 32Mb QSPI NOR Flash

• Wi-Fi 11b/g/n/ac + Bluetooth 5.0 certified module

• 2Kb I2C EEPROM

• Power management devices

• Commercial and industrial temperature grade support.

Supporting Products

The following products are provided by SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard IIOT

• SolidSense AIOT

Description

Block Diagram

The following figure describes the RZ/V2N Blocks Diagram.

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Features Summary

Listed below are the SOM’s main features. Notice that some of the features are multiplexed pinout (please refer to the pin mux table below and the Renesas’s data sheets):

• Renesas’s RZV2N series SoC (Dual ARM® Cortex™ A55 Processor, up to 1.8 GHz)

• Cortex-M33 (200MHz) subsystem processor.

• AI accelerator; DRP-AI

• Up to 8GByte (Default) LPDDR4x memory and up to 12.8GB/s

• Eight bits eMMC 5.1 memory (Boot)

• 2Kb I2C EEPROM.

• 8Mb QSPI NOR Flash (Boot).

• 4-lanes MIPI-DSI interface

• 3D graphics engine (Arm Mali-G31).

• Video codec (H.264/265).

• ISP - Mali-C55 (Optional)

• Two 4-lanes MIPI CSI-2

• Dual 10/100/1000 Mbps Ethernet PHY

• Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata's certified module

• USB3.2 (Gen2, Host)

• USB2.0 (Host/Device)

• Four bits SDIO interface (BtB connectors, NOT bootable)

• Single eSPI interface.

• Up to four Serial interfaces.

• Up to 2 CAN-FD.

• Power:

  • A single 5.0V input using B-t-B connector.

  • 1.8V/1A output to support carrier's digital interfaces.

  • RAA215300-HA7 PMIC

Core System Components

RZV2N SoC Family

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZV2N SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support.

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Memories

The RZV2N SOM supports varieties of memory interfaces for booting and data storage. The following figure describes the RZV2N memory interfaces.

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LPDDR4x

• Up to 8GB memory space.

• 32 Bits data bus.

• Up to 3200 MT/s.

• In line ECC (16 ECC regions) supported (support for error detection interrupts)

• Auto-refresh, self-refresh, and IO retention supported.

• Memory access protection for secure regions using TZC-400 (Arm® TrustZone® supported).

eMMC

• Up to 128GB memory space.

• 8 Bits data bus.

• Support MMC standard, up to version 4.5.1.

• Supports High-speed, HS200 transfer modes.

• uSDHC-0.

• Can be used as BOOT NVM **

Micro-SD (Carrier)

• Optional on Carrier board

• uSDHC-0.

• Implements 4 data bits.

• Support SD/SDIO standard, up to version 3.0.1.

• SD, SDHC and SDXC SD memory card access supported.

• Default, high-speed, UHS-I/SDR50, SDR104 transfer modes supported

• Can’t be used as BOOT NVM (UBOOT).

Quad Serial NOR Flash (SOM)

• Can be configured as 1/2/4-bit operation.

• Compliant with the xSPI protocol

• Support both SDR (66MHz) mode and DDR (50MHz) mode

• No reset

• QSPIA/nSS0.

• Can be used as BOOT NVM **

EEPROM (SOM)

• 2Kb EEPROM

• ON-Semi’s CAT24AA02TDI or compatible

• I2C8

• Address 0X50 (7 bits format)

• Stores SOM’s configurations.

Serial NOR Flash (Carrier)

• Optional on Carrier board

• 1 bit data bus.

• eSPIA/nSS0

• Can be used as BOOT NVM **

FTDI (Carrier)

• USB to UART can be used for SW download to memories.

Dual 10/100/1000 Mbps Ethernet PHY

RZV2N SOM supports dual Giga Ethernet interfaces.

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• RGMII interface.

• 802.3 Ethernet interface for 1000BASE-t, 100BASE-TX, and10BASE-T.

• MaxLinear's MxL86110I PHY.

• Auto-MDIX and polarity correction

• Energy-Efficient Ethernet (EEE) and power down mode.

• 10k byte jumbo frame support.

WI-FI (802.11a/b/g/n/ac) and BT 5.0 (Murata's Certified Module)

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The WI-FI & BT module is Murata’s 1MW module Based on Cypress CYW43455. hip. The WI-FI main features are:

• Operate at ISM frequency Band (2.4/ 5 GHz).

• IEEE Standards Support 802.11ac, 802.11a, 802.11b, 802.11g and 802.11n.

• WI-FI over SDIO-2 interface.

• BT 5.0 BR/EDR/LE.

• BT over UART-0 Interface.

• Global certification.

External Interfaces

General

The SOM incorporates three Hirose DF40 board-to-board headers.

The selection of the Hirose DF40 is due to the following criteria:

• Miniature (0.4m pitch)

• Highly reliable manufacturer

• Availability (worldwide distribution channels)

• Excellent signal integrity (supports 6Gbps)

  • Please contact Hirose or SolidRun for reliability and test result data.

• Mating height of between 1.5mm to 3.0mm. RZV2N SOM’s headers are fixed, the final mating height is determined by carrier implementation

Supported Interfaces

USB-3.0 and USB-2.0

The RZV2N supports a single USB3.0 and a single USB2.0 interface. The following figure describes the USB interfaces.

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USB 3.0

• Compliant with USB3.2 Gen2

• HOST

• Maximum rate: 10 Gbps

USB 2.0

• Compliant with USB2.0

• HOST/Function

• Support for On-The-Go (OTG) functionality

MIPI CSI

The following figure describes the CSI interface.

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• Support two MIPI CSI-2 V2.1

• Support MIPI D-PHY V1.2 (80 Mbps to 2100 Mbps/lane)

• Maximum bandwidth: 2.1 Gbps per lane

• Support for the throughput up to 4K RAW12 30 fps

• Support for 4 virtual channels selected from VC0 to VC15.

MIPI DSI

The following figure describes the DSI interface.

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The DSI main features are:

• Display Serial Interface Version 1.3.1.

• Supports up to Full HD (1920 × 1200), 60 fps (RGB888)

• Maximum Bandwidth: 1.5 Gbps per lane, 4 data lanes.

• Support Output Data Format: RGB666 / RGB888.

• Supports 1, 2, 3 and 4 lane configurations.

PCIe 3.0

The following figure describes the PCIe interface

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• Single PCIe Gen-3 controller

• PCI Express Gen1 (2.5 GT/s)/Gen2 (5.0 GT/s)/Gen3 (8.0 GT/s)

• Root Complex (RC) / Endpoint (EP) Applications, Type 0/1 Configuration Register

• Lane implementation x2 / x1

• Clock generator can be bypassed in EP mode

Audio

The following figure describes the CSI interface.

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• Asynchronous sampling rate converter unit (SCU) (up to 192 kHz)

• DMAC for Audio (ADMAC) is available to transfer audio formats of I2S with SCU

• Flexible audio clock generator (ADG) for audio functions

• I2S (TDM) input/output interfaces (half-duplex 10 ch.; full-duplex 5 ch.)

CAN-FD

Up to 6 CANFD* interfaces are available. The following figure describes the CAN interfaces.

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The CAN main features are:

• Supports two interface modes, classical CAN mode and CANFD mode.

• CAN-FD ISO 11898-1 (2015) compliant.

• Support for up to 8 MHz with payload transfer.

Connector’s Signal Description

J5001

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J7

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J9

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Power & Reset

Power Architecture

The RZV2 SOM power source is a single 5V source. It uses Renesas’s PMIC RAA215300A2GNP#HA7 to source some of the SOM's power rails and for power sequencing.

Other power rails are supported by discreet power sources. VDD_0V8/12A is supported by TI’s TPS62872 and DDR_0V6 is supported by TI’s TPSM82823.

The main features of power architecture are:

• Single 5V power source.

• Renesas’s RAA215300-HA7 source the RZV2N power rails.

• 1.8V output up to 0.6A (Need to calculate system and SOM power).

• Power up sequence is supported by the PMIC configuration.

Reset

The PMIC generates the POR. A reset signal (PMIC_CRST_IN#) from the carrier board can generate a POR.

The PMIC supports a Power ON/OFF (*) signal that can disable/enable all power signals beside RTC.

The PMIC supports an RTC that can be powered by a battery(J7-63).

POWER CONSUMPTION

RZ/V2N Power Table

Integration Manual

Power Up Sequence

The RZV2N is sourced by a single 5V input. All power sequences are supported by the PMIC.

When using the SOM 1.8V output there is no need to consider its power sequence. If an external power source is used for the 1.8V, it needs to be power according to the power sequence rules. (See RZV2N datasheet for details)

Booting Options

Strap pins Booting

The RZV2N boosts from different NVM or serial interfaces according to an external's resistors setting. The boot configuration is set by the two configuration signals (MD0, MD1). Below is a table describing the configuration modes.

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Mechanical Description

Following is a diagram of the TOP VIEW of the RZ/V2N.

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SOM Version Changes:

Documentation

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