Content Comparison

Revisions and Notes 

Introduction

This User Manual relates to the SolidRun’s RZG2 series, which includes

Introduction

This User Manual relates to the SolidRun’s RZG2 series, which includes

• RZG2LC Dual core ARM A55 (1.2GHz) w Cortex-M33 (200MHz)

• RZG2UL Single core ARM A55 (1.0GHz) w Cortex-M33 (200MHz)

Overview

The SolidRun’s RZG2L RZ/G2LC family is a high-performance 64-Bit Renesas RZ/G2 Based SOMs with Integrated GPU for Next-Gen Human-Machine Interfaces.

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support.

Highlighted Features

• Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).

• Renesas’s SoC supports Solo and DUAL versions.

• Up to Dual Cortex A55 and up to 1.2GHz

• Cortex-M33 subsystem processor supports real time tasks.

• High security engines.

• A single Ethernet interfaces.

• Up to two CAN interfaces.

• High industrial reliability with in-line ECC on DDR4 and on on-chip RAM.

• Single MIPI-CSI and single MIPI-DSI (NO encoder/decoder)

• Two USB 2.0.

• DDR4 memory in x16 configurations supports up to 2GB and up to 3.2GT/s.

• Up to 128GB eMMCUp to 64GB eMMC (HighSpeed Mode, up to 52MHz).

• Wi-Fi 11b/g/n + Bluetooth 5.2 certified module

• 1Mb QSPI NOR Flash

• 1Kb I2C EEPROM

• Real time Clock and a rechargeable battery

• Power management devices

• Commercial and industrial temperature grade support.

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard PulseRipple – A board computer that incorporates the SOM retains the same Android and different Linux distributions while adding extra hardware functionalities and access to the hardware.

Description

Block Diagram

The following figure describes the RZ/G2LC Blocks Diagram.Image Removed

Image Added

Features Summary

Following are the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the Renesas’s data sheets):

• Renesas’s RZG2 series SoC (Dual/Single ARM® Cortex™ A55 Processor, up to 1.2 GHz)

• Cortex-M33 (200MHz) subsystem processor.

• Up to 2GByte DDR4 memory and up to 3.2GT/s

• Eight bits eMMC 5.1 (HS Speed Mode) memory or a four bits SD interface

• 1Kb I2C EEPROM.

• 8Mb QSPI NOR Flash

• 4-lanes MIPI-DSI interface

• 4-lanes MIPI CSI-2

• Single 10/100 Mbps Ethernet PHY

• Wi-Fi (802.11a/b/g/n) + BT (5.2) Murata's certified module

• Two USB 2.0 Host and Device

• Single eSPI interface.

• Up to four Serial interfaces.

• Up to 2 CAN-FD.

• RTC w a rechargeable battery

• Power:

o A single 5.0V input using B-t-B connector

o 3.3V/1A output to support carrier's digital interfaces.

o 1.2V/0.5A output

o RAA215300 PMIC

Core System Components

RZ/G2LC SoC

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support.

A verified Linux Package (VLP) reduces cost and simplifies design

MEMORIES

The RZG2L SOM supports varieties of memory interfaces for booting and data storage. The following figure describes the RZG2L memory interfaces.

DDR4

• Up to 2GB memory space.

• 16 Bits data bus.

• Up to 3600 MT/s.

• ECC function for single-bit and double-bit error reporting, single-bit error correction, and programmable removal of ECC storage

• Support various low power modes, clock, and power gated operation.

• Support Self-Refresh mode.

eMMC and SD NAND Memory

SD0 of the RZG2LC/UL can be configured as an 8 bits -bit eMMC interface or a 4 bits -bit SDIO. Configuration can be done during the boot process (Boot strap pins) or by SW.

Selecting SD0’s physical connection (eMMC or uSD card) is done by an analog switch.

 eMMC

• Up to 128GB 64GB memory space.

• 8 Bits data bus.

• Support MMC standard, up to version 4.5.1.

• Supports High-speed, HS200 transfer modes Mode (up to 52MHz)

• uSDHC-0.

• Can be used as BOOT NVM **

Micro-SD (Carrier)

• Optional on Carrier the carrier board

• uSDHC-0.

• Implements 4 data bits.

• Support SD/SDIO standard , up to version 3.0.

• SD, SDHC, and SDXC SD memory card access supported.

• Default, high-speed, UHS-I/SDR50, and SDR104 transfer modes supported

• Can be used as BOOT NVM **

Quad Serial NOR Flash (SOM)

• Each channel can be configured as a 1/2/4-bit operation.

• Support both SDR (66MHz) mode and DDR (50MHz) mode

• No reset

• QSPIA/nSS0.

• Can be used as BOOT NVM **

 EEPROM (SOM)

• 1Kb EEPROM

• ON-Semi’s CAT24AA01TDI or compatible

• I2C0

• Address 0X50 (7 bits format)

• Stores SOM’s configurations.

Serial NOR Flash (Carrier)

• Optional on Carrier carrier board

• 1 bit data bus.

• eSPI1/nSS0

• Can be used as BOOT NVM *

10/100

Mbps Ethernet PHY

 The SOM supports single fast Ethernet interfaces.

Image Added

• RGMII interface.

• 802.3 Ethernet interface for 100BASE-TX, and10BASE-T.

• Analog Device's ADIN1200 PHY.

• EEE in accordance with IEEE 802.3az

• Start of packet detection for IEEE 1588 time stamp timestamp support

• 139 mW for 100BASE-TX

WI-FI (802.11A/B/G/N) AND BT 5.2 (MURATA'S CERTIFIED MODULE)

WI-FI & BT

 The WI-FI & BT module is Murata’s 1YN module Based on Cypress CYW43439W. hip. The WI-FI main features are:

• Operate at ISM frequency Band (2.4)

• IEEE Standards Support 802.11a, 802.11b, 802.11g and 802.11n

• WI-FI over SDIO-1 interface

• BT 5.2 BR/EDR/LE

• BT over UART-2 Interface

• Global certification.

External Interfaces

General

The SOM incorporates three Hirose DF40 board-to-board headers.

The selection of the Hirose DF40 is due to the following criteria:

• Miniature (0.4m pitch)

• Highly reliable manufacturer

• Availability (worldwide distribution channels)

• Excellent signal integrity (supports 6Gbps)

• • Please contact Hirose or SolidRun for reliability and test result data.

• Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). RZG2LC/UL SOM’s headers are fixed, the final mating height is determined by carrier implementation

USB-2.0

The RZG2LC/UL supports two USB2.0 interfaces. The following figure describes the USB interfaces.

The USB USB’s main features are:

• Single USB2USB 2.0 OTG/DRD(Host/Function) interface (USB0)

• Single USB2USB 2.0 Host interface (USB1).

• Support mode: High-Speed(480Mbps)/Full-Speed(12Mbps)/Low-Speed(1.5Mbps).

• OTG function (Rev2.0).

• Battery Charging function.

• B2B Connector’s Signal Description

• DRD(Dual-Role-Device) function (Static switch between Host and Function).

• Power control signal signals are not part of the USB module, any available GPIO can be used.

MIPI CSI

The following figure describes the CSI interface.

Image Added

• Supports MIPI CSI-2 V2.1 and MIPI D-PHY V2.1 (80 Mbps ~ 1500 Mbps)..

• Maximum image size: 5 M pixels.

• Minimum image size: QVGA (320 × 240) ＝ 76.8 K pixels.

• Maximum number of valid pixels in the horizontal direction: 2800 pixels.

• Maximum number of valid pixels in the vertical direction: 4095 lines

• Support 1/2/4 lanes.

• Support 4 Virtual Channel.

MIPI DSI

The following figure described describes the DSI interface.

Image Added

The DSI main features are:

• Display Serial Interface Version 1.3.1.

• Support up to Full HD (1920 × 1080), 60 fps (RGB888).

• Maximum Bandwidth: 1.5 Gbps per lane, 4 data lanes.

• Support Output Data Format: RGB666 / RGB888.

• Supports 1, 2, 3 and 4 lane configurations.

• Support for Virtual Channel

Audio

Up to 3 serial sound interface (SSIF-2) transmits and receives audio data to and from various devices that are compatible with I2S format, monaural format and TDM format.

The Audio main features are:

• Master/slave

• Full-duplex communication is available in interfaces 0, 1.

• Half-duplex communication is only available in interface 2.

• I2S format, Monaural format and TDM format.

• MSB first, data can be left-justified or right-justified.

UART

Up to 4 UART interfaces. The following figure describes the UART interfaces.

The UART interfaces interface's main features are:

• UART 2 is connected directly to the WI-FI/BT Modem to support the BT. It is available on the SOM B-t-B connector When the WIFI is not assembled.

• UART 0 supports TX, RX and is used as terminal interface

• UART 1 Supports supports TX, RX, CTS and RTS.

• UART 3 support supports TX and RX.

• Selectable bit rate with an on-chip baud rate generator.

SPI

Up to 3 SPI interfaceinterfaces. The following figure describes the eSPI interface.

• Single chip select nSS0.

• Master/Slave configurable.

• Switching of the polarity of the serial transfer clock.

• Switching of the clock phase of serial transfer.

• Transfer bit-length is selectable as 8, 16, or 32 bits.

I2C

Up to 4 I2C Interfaces. The following figure describes the I2C interfaces.

The I2C main features are:

• I2C-2 is used only on the SOM. It is connected to the PMIC.

• I2C-0 is available on the connector and connected to the SOM’s EEPROM.

• I2C-1 and I2C3 are available on the BtB connectors.

• I2C bus format or SMBus format.

• Master mode or slave mode selectable

• Up to 1 Mbps.

• Up to three slave-address settings can be made.

• Internal time-out function is capable of detecting long-interval stop of the SCL (clock signal).

uSD

The uSD interface is multiplexed with the eMMC interface. Only one of them is available.

CAN-FD

Up to 2 CANFD interfaces are available. The following figure describes the CAN interfaces.

The CAN main features are:

• Supports two interface modes, classical CAN mode and CANFD mode.

• ISO11898-1 compliant.

• Maximum 1 Mbps in classical CAN mode.

• Nominal bit rate: max.1 Mbps, data bit rate: max. 4 Mbps in CANFD mode.

CONNECTOR’S SIGNAL DESCRIPTION

J5001

J7

J9

mikroBUS

HBP 2.4

RZG2LC 1.0

MIKROBUS (J8-2)

RZ_SSI0_RXD

MIKROBUS (J8-3)

RZ_RSPI1_SSL

MIKROBUS (J8-4)

RZ_RSPI1_CK

MIKROBUS (J8-5)

RZ_RSPI1_MISO

MIKROBUS (J8-6)

RZ_RSPI1_MOSI

MIKROBUS (J10-1)

RZ_SCIF1_CTS

MIKROBUS (J10-2)

RZ_SCIF1_RTS

MIKROBUS (J10-3)

RZ_SCIF1_RXD

MIKROBUS (J10-4)

RZ_SCIF1_TXD

MIKROBUS (J10-5)

RZ_RIIC0_SCL

MIKROBUS (J10-6)

RZ_RIIC0_SDA

Power & Reset

The RZG2LC/UL SOM power source is a single 5V source. It uses Renesas’s PMIC to source all the SOM's power rails. The following figure describes the power architecture.

Image Removed

The power architecture main features are:

• Single 5V power source.

• Renesas’s RAA215300 source the RZG2LC/UL power rails.

• 3.3V output up to 1A (Need to calculate system and SOM power).

• Power up sequence is supported by the PMIC configuration.

SOM Revision and Notes

Image Added

mikroBUS

Power & Reset

The RZG2LC/UL SOM power source is a single 5V source. It uses Renesas’s PMIC to source all the SOM's power rails. The following figure describes the power architecture.

Image Added

The power architecture main features are:

• Single 5V power source.

• Renesas’s RAA215300 source the RZG2LC/UL power rails.

• 3.3V output up to 1A (Need to calculate system and SOM power).

• Power up sequence is supported by the PMIC configuration.

Power Consumption

RESET

The PMIC generate the POR. A reset signal (PMIC_CRST_IN#) from the carrier board can generate a POR.

The PMIC supports a Power ON/OFF signal that can disable/enable all power signals beside RTC.

The PMIC supports an RTC that can be powered by a battery (on SOM).

RZG2LC/UL INTEGRATION MANUAL

POWER UP SEQUENCE

The RZG2LC/UL is sourced by a single 5V input. All power sequences are supported by the PMIC.

When using the SOM 3.3V output there is no need to consider its power sequence. If an external power source is used for the 3.3V, it needs to be power according to the power sequence rules. (See RZG2LC/UL datasheet for details)

BOOTING OPTIONS

Strap pins Booting

The RZG2LC/UL boost from different NVM or serial interfaces according to an external's resistors setting. The boot configuration is set by the three configuration signals, below is a table describing the configuration modes

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Image Added

I2C INTERFACES

The RZG2LC/UL uses I2C2 (PMIC) interfaces for its internal configurations.

GPIO INTERFACES

The RZG2LC SOM uses some GPIO signals for its internal controls. The following table describes the GPIO allocation.

Mechanical Description

Following is a diagram of the TOP VIEW of the RZG2LC/UL.

Documentation

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