...
(*) Contact SolidRun for this option - requires assembling 100MHz reference clock for SD1 PLLF instead of default 161.13285MHz reference clock
(*) As a self-service the customer can modify the default REFDES U10 that is 161.13285MHz differential clock which is Epson PN X1G004251012100 to Epson PN SG3225EAN 100.000000M-KEGA3. The placement of U10 is as below - (pin 1 marked in red dot) -
...
SERDES block #2 (SD2)
Protocol | Lane 0 10G-KR0 | Lane 1 10G- KR1 | Lane 2 10G-KR2 | Lane 3 10G-KR3 | Lane 4 PCIe16 | Lane 5 PCIe17 | Lane 6 PCIe18 | Lane 7 PCIe19 |
0 | off | off | off | off | off | off | off | off |
1 | PCIe.3 x 2 (gen 1,2) | SATA.1 | SATA.2 | PCIe.4 x4 (gen 1,2) | ||||
2 | PCIe.3 x8 | |||||||
3 | PCIe.3 x4 | PCIe.4 x4 | ||||||
4 | PCIe.3 x4 (gen 1,2) | PCIe.4 x2 (gen 1,2) | SATA.1 | SATA.2 | ||||
5 | PCIe.3 x4 | SATA.3 | SATA.4 | SATA.1 | SATA.2 | |||
6 | PCIe.3 x4 (gen 1,2) | SGMII.15 | SGMII.16 | USXGMII / XFI.13 | USXGMII / XFI.14 | |||
7 | PCIe.3 x1 (gen 1,2) | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x1 (gen 1,2) | SGMII.16 | USXGMII / XFI.13 | USXGMII / XFI.14 |
8 | X | X | SATA.1 | SATA.2 | SATA.3 | SATA.4 | USXGMII / XFI.13 | USXGMII / XFI.14 |
9 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | SGMII.15 | SGMII.16 | SGMII.13 | SGMII.14 |
10 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x4 | |||
11 | PCIe.3 x1 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x1 | SGMII.16 | SGMII.13 | SGMII.14 |
12 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x2 (gen 1,2) | SATA.1 | SATA.2 | |
13 | PCIe.3 x4 | PCIe.2 x2 | SGMII.13 | SGMII.14 | ||||
14 | PCIe.3 x2 | SGMII.17 | SGMII.18 | PCIe.2 x2 | SGMII.13 | SGMII.14 | ||
...