LX2162A SOM Hardware User Manual
- SolidRun
- Rabeeh Khoury
- Ilan Braun (Unlicensed)
Revisions and Notes
Date | Owner | Revision | Notes |
Mar 27, 2022 | Rabeeh Khoury | 1.0 |
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May 15, 2023 | Rabeeh Khoury | 1.1 |
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Table of Contents |
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No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.
Introduction
This document is intended for hardware engineers that are willing to integrate
LX2162A SOM module from SolidRun ltd.
The document provides details with regards LX2162A module rev 1.0.
Below are two pictures of the SOM; the first is the top side where most of the heat is generated; and the second is from the bottom side where it connects to a carrier board -
Specifications
| LX2082A | LX2122A | LX2162A |
CPU Details | NXP Layerscape LX2082A | NXP Layerscape LX2122A | NXP Layerscape LX2162A |
CPU Speed | 2.0GHz Commercial | 2.0GHz Commercial | 2.0GHz Commercial |
RAM | Single channel | Single channel | Single channel |
Internal Storage | 8GB eMMC (other ordering options available) | 8GB eMMC (other ordering options available) | 8GB eMMC (other ordering options available) |
External Storage Support | SD | SD | SD |
Ethernet | Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) 1GbE with PHY | Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) 1GbE with PHY | Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) 1GbE with PHY |
USB 3.0 | 1 | 1 | 1 |
PCIe | 8 (Gen 3 – 2 controllers)* | 8 (Gen 3 – 2 controllers)* | 8 (Gen 3 – 2 controllers)* |
I2C | 4 | 4 | 4 |
UART | 2 | 2 | 2 |
GPIO | ✔ | ✔ | ✔ |
SATA | 4xGen 3(*) | 4xGen 3(*) | 4xGen 3(*) |
Security | NXP Layerscape Secure Boot | NXP Layerscape Secure Boot | NXP Layerscape Secure Boot |
SD | 1 | 1 | 1 |
JTAG | ✔ | ✔ | ✔ |
OS Support | Linux | Linux | Linux |
Size | 55 x 48 mm | 55 x 48 mm | 55 x 48 mm |
Interface | 3 x Hirose DF40 connectors | 3 x Hirose DF40 connectors | 3 x Hirose DF40 connectors |
Main Voltage | 12V | 12V | 12V |
I/O Voltage | 3.3V/1.8V | 3.3V/1.8V | 3.3V/1.8V |
Temperature | Commercial: 0°C to 70°C | Commercial: 0°C to 70°C | Commercial: 0°C to 70°C |
Humidity | Humidity (non-condensing): 10% – 90% | Humidity (non-condensing): 10% – 90% | Humidity (non-condensing): 10% – 90% |
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(*) Configurable SD2 SERDESs based on NXP LX2162A processor specifications.
Overview
LX2162A SOM is a highly integrated SOM module based on NXP’s LX2162A SoC.
The SoC highlights are up to 2.0GHz 16 x Cortex A72 Arm cores, DDR4 2900 MT/s up to 16 GB capacity with ECC and 12 high speed SERDESes.
The module integrates the following features –
LX2162A SoC (up to 2.0GHz).
On-board single controller supports up to 16GByte DDR4 2900Mtps memory with and without ECC.
Single 12V DC-input is required.
Description
Block Diagram
The following figure describes the LX2162A SOM Blocks Diagram.
Simplified Schematics
Following is a link to that simplified schematics of the board : LX2162A COM Simplified Schematics
LX2162A SOM simplified schematics is intended for the following audience –
Software and firmware engineers that enables them to understand the IO and signal connectivity of the SOM design.
Hardware engineers that are willing to use the SOM and build their own development board.
Module dimensions and board to board header orientation
SOM bottom side DXF file - use attached dxf file for board dimensions, mounting holes and board to board connectors location
*note the board to board pin numbers and keep in mind this is bottom view
Module Max Power Consumption Measurements
Worst case scenario measured, power consumption wise was ~35W on the following scenario -
SOM attached to a simple carrier baseboard
Measured the 12v power rail coming to the whole system
Running 16 threads cpuburn application or memtester application on all cores
CPU junction temperature set to max at 105c
Test excludes SERDES connection, so additional 2-3W for SERDES connections must be taken into account.
SERDES configuration
LX2162A has 2 configurable SERDES blocks named SD1, and SD2.
SERDES 1 block has 4 SERDESes, and SERDES 2 block has 8 SERDESes that can be configured by protocol number. The protocol numbers are limited and can be selected from the following configurations –
SERDES block #1 (SD1)
Protocol | Lane 0 10G-KR0 | Lane 1 10G- KR1 | Lane 2 10G-KR2 | Lane 3 10G-KR3 |
0 | off | off | off | off |
1 (*) | PCIe.1 x4 | |||
2 (*) | SGMII.3 | SGMII.4 | SGMII.5 | SGMII.6 |
3 | USXGMII / XFI.3 | USXGMII / XFI.4 | USXGMII / XFI.5 | USXGMII / XFI.6 |
9 (*) | PCIe.1 x1 | SGMII.4 | SGMII.5 | SGMII.6 |
11 (*) | PCIe.1 x2 | SGMII.5 | SGMII.6 | |
15 | 50GE.1 | 50GE.2 | ||
16 | 50GE.1 | 25GE.5 | 25GE.6 | |
17 | 25GE.3 | 25GE.4 | 25GE.5 | 25GE.6 |
18 | USXGMII / XFI.3 | USXGMII / XFI.4 | 25GE.5 | 25GE.6 |
20 | 40GE.1 | |||
(*) Contact SolidRun for this option - requires assembling 100MHz reference clock for SD1 PLLF instead of default 161.13285MHz reference clock
(*) As a self-service the customer can modify the default REFDES U10 that is 161.13285MHz differential clock which is Epson PN X1G004251012100 to Epson PN SG3225EAN 100.000000M-KEGA3. The placement of U10 is as below - (pin 1 marked in red dot) -
SERDES block #2 (SD2)
Protocol | Lane 0 10G-KR0 | Lane 1 10G- KR1 | Lane 2 10G-KR2 | Lane 3 10G-KR3 | Lane 4 PCIe16 | Lane 5 PCIe17 | Lane 6 PCIe18 | Lane 7 PCIe19 |
0 | off | off | off | off | off | off | off | off |
1 | PCIe.3 x 2 (gen 1,2) | SATA.1 | SATA.2 | PCIe.4 x4 (gen 1,2) | ||||
2 | PCIe.3 x8 | |||||||
3 | PCIe.3 x4 | PCIe.4 x4 | ||||||
4 | PCIe.3 x4 (gen 1,2) | PCIe.4 x2 (gen 1,2) | SATA.1 | SATA.2 | ||||
5 | PCIe.3 x4 | SATA.3 | SATA.4 | SATA.1 | SATA.2 | |||
6 | PCIe.3 x4 (gen 1,2) | SGMII.15 | SGMII.16 | USXGMII / XFI.13 | USXGMII / XFI.14 | |||
7 | PCIe.3 x1 (gen 1,2) | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x1 (gen 1,2) | SGMII.16 | USXGMII / XFI.13 | USXGMII / XFI.14 |
8 | X | X | SATA.1 | SATA.2 | SATA.3 | SATA.4 | USXGMII / XFI.13 | USXGMII / XFI.14 |
9 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | SGMII.15 | SGMII.16 | SGMII.13 | SGMII.14 |
10 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x4 | |||
11 | PCIe.3 x1 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x1 | SGMII.16 | SGMII.13 | SGMII.14 |
12 | SGMII.11 | SGMII.12 | SGMII.17 | SGMII.18 | PCIe.4 x2 (gen 1,2) | SATA.1 | SATA.2 | |
13 | PCIe.3 x4 | PCIe.2 x2 | SGMII.13 | SGMII.14 | ||||
14 | PCIe.3 x2 | SGMII.17 | SGMII.18 | PCIe.2 x2 | SGMII.13 | SGMII.14 | ||
Notice: By default SD2 PLLS is assembled as onboard 156.25MHz and an external 100MHz reference clock (HCSL) is required to be supplied by the carrier board. There is an option to order with an integrated 100MHz reference clock but will require special order from SolidRun.
Pinout
J3 Header
Notes | Driving IC | IC ball number | Schematics Pin Name | Pin Number | Pin Number | Schematics Pin Name | IC ball number | Driving IC | Notes |
|---|---|---|---|---|---|---|---|---|---|
Can be floated, or pulled to GND until carrier board powers are valid |
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| PWR_OK | 2 | 1 | EVT0_B | T4 | 1.8V, GPIO_3[12], 4.7K Pull-up | SMB_ALERT# |
Connect to RTC battery source |
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| VBAT | 4 | 3 | EVT1_B | T6 | 1.8V, GPIO_3[13], 4.7K Pull-up | THRM# |
Output from SOM. Can be used by carrier board up to 600mA |
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| 5V | 6 | 5 | EVT2_B | U5 | 1.8V, GPIO_3[14], 4.7K Pull-up |
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Output from SOM. Can be used by carrier board up to 600mA |
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| 5V | 8 | 7 | EVT4_B | AA3 | 1.8V, GPIO_3[16], 4.7K Pull-up |
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PROC_TMS | LX2162A | E21 | DUT_TMS | 10 | 9 | EVT3_B | Y4 | 1.8V, GPIO_3[15], 4.7K Pull-up |
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PROC_TCK | LX2162A | E23 | DUT_TCK | 12 | 11 | TA_BB_VDD |
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Output from SOM. Can be used by carrier board up to 300mA |
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| 3.3V | 14 | 13 | TMP_DETECT_B | Y6 | 1.8V, 4.7K Pull-up |
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PROC_TDI | LX2162A | F20 | DUT_TDI | 16 | 15 | OVDD |
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| 1.8v Output from SOM. Can be used by carrier board up to 300mA |
Control the main DC-DC controller |
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| I2C_MASTER_SCL | 18 | 17 | V_2.5 |
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| Output from SOM. Can be used by carrier board up to 600mA |
Control the main DC-DC controller |
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| I2C_MASTER_SDA | 20 | 19 | V_2.5 |
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PROC_TDO | LX2162A | E19 | DUT_TDO | 22 | 21 | I2C1_SCL_3p3 |
| NTSX2102GD, 2.2K Pull-up |
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Can be used to program the internal efuses |
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| TA_PROG_SFP | 24 | 23 | I2C1_SDA_3p3 |
| NTSX2102GD, 2.2K Pull-up |
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FTM1_CH4 / GPIO_3[0] | 1.8V, 4.7K Pull-up | R5 | PROC_IRQ0 | 26 | 25 | SPI_D0_1v8 |
SolidRun Ltd.