LX2160A COM Hardware User Manual

Revisions and Notes 

Introduction

This document is intended for hardware engineers that are willing to integrate

LX2160A COM express type 7 module from SolidRun ltd.

The document provides details with regards LX2160A module rev 1.3, 1.4, 1.5 and 1.6.

Specifications

Overview

LX2160A COM express type 7 is a highly integrated COM modules based on NXP’s LX2160A SoC.

The SoC highlights are up to 2.0GHz 16 x Cortex A72 Arm cores, two DDR4 controllers up to 3200Mtps and 24 high speed SERDESes.

The module integrates the following features –

1. LX2160A SoC (up to 2.0GHz).

2. Two SO-DIMM DDR4 connected to the two DDR contorllers. Each SO-DIMM supports up to 32GByte SO-DIMM DDR4 3200Mtps memory with and without ECC, registered or non-registered; total up to 64GByte system memory.

3. Single 12v DC-input is required.

Description

Block Diagram

The following figure describes the LX2160A COM express type 7 Blocks Diagram.

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Simplified Schematics

Following is a link to that simplified schematics of the board : LX2160A COM Simplified Schematics

LX2160A COM express type 7 simplified schematics is intended for the following audience –

1. Software and firmware engineers that enables them to understand the IO and signal connectivity of the COM express design.

2. Hardware engineers that are willing to use the COM express and build their own development board. This document completes the CEx7 LX2160A reference manual from description of signal and implementation wise.

S-Parameters

Browse below in the Documentation section in other files section to download LX2160A-CEX7 S-parameters.

The 25 GbE files refer to the 10G KR signals – total 32 ports model up to 20GHz and the second PCIe file refers to all other SERDESes while the model is up to 6GHz.

The S-parameters models includes the PCB extraction with the COM express header AND receptacle based on models from EPT.

Module Power Consumption Measurements

The following power consumption measurements were conducted on the following setup –

1. HoneyComb LX2 mini-ITX motherboard with pico-psu ATX power source

2. LX2160A COM express type 7 module connected running at 2GHz core, 700 MHz fabric and 3200Mtps DDR

3. Two SO-DIMM DDR4 at 3200Mtps (total 2x8GB = 16GByte system memory)

4. During the tests an 1.3Watt fan mounted on the processor. The idle, memtester and first cpu-burn power measurements below includes those 1.3Watt, the measurements with die temperature of 65c and above has the fan disconnected.

5. Temperature measurement was done using Linux ‘sensors’ commands, that reads both the PCB (print side of the board away from the center) and the processor die temperature.

6. Software running is based on NXP LSDK-19.06 software release.

7. A 12v PSU is connected to a pico-psu (12v to ATX); and power is measured by multiplying the current and the voltage on the 12v input rail.

Since the measurement is done on the input of the pico-psu; the SoC consumption all together with the DDR and all the DC-DC losses are measured too.

Maximum Current Consumption

The LX2160A type 7 uses only the 12v power rail to supply it’s internal components.

The user of this module must make sure that the 12v power rail provided to the COM can sustain 5A, i.e. total 60W.

Notice the above section on power measurement using memtester and cpuburn applications which is worst case scenario of ~40@ when the core junction is at 105c; taking into account different SO-DIMMs used and variance in processor leakage due to silicon manufacturing environments, we recommend to design the carrier board to sustain those 5A on the 12V rail.

PCIe Lane Numbers and Bucket Grouping

Following is the bucket grouping of the different PCIe lanes.

Bucket B1 – lanes #0 .. #7

There is a single configuration in this bucket –

x4 PCIe lanes 0,1,2,3 connected to controller #3 (SERDES SD2 lanes 0,1,2,3)

x2 PCIe lanes 4,5 connected to controller #4 (SERDES SD2 lanes 4,5)

PCIe lanes 6,7 are NC

• Notice that it is possible to gang PCIe lanes 0..5 with SATA0 and SATA1 and which makes all SD2 lanes 0..7 and have a single x8 gen3 controller #3. In this configuration the on COM module DC bias serial capacitors are required to be changed to 220nF instead of 10nF (contact SolidRun for more information)

Bucket B2 – lanes #8 .. #15

There are two possible configurations in this bucket –

1. 2 times x4 – Lanes 8 to 11 connected to controller #5 and lanes 12 to 15 connected to controller #6.

2. 1 time x8 -Lanes 8 to 15 are connected to controller #5

Bucket B3 – lanes #16 .. #23

There is a single configuration in this bucket –

1. Up to 1 time x4 – lanes 16 .. 19 on controller #2.
   Lanes 20 to 23 are NC.

• Notice that this configuration highly depends on the SD1 SERDES protocol number configuration. Please follow SD1 protocol number configuration in this document that explains how those lanes are affected.

Bucket B4 – lanes #24 .. #31

All lanes in this bucket are NC.

SERDES configuration

LX2160A has 3 SERDES blocks named SD1, SD2 and SD3.

SERDES block #1 (SD1)

SERDES block #1 (SD1) has the most different options to configure from. By default the board is assembled with PLLF=161.1328125MHz and PLLS=100MHz, spread spectrum disabled.

In order to swap both PLLF and PLLS to be 100MHz:

• Move C996 and C997 to C80 and C81 (same value 100nF low ESL 0402 capacitor). This will move the 161.1328125MHz from PLLF to PLLS

• Move R383 and R384 to R381 and R382 (zero ohm 0402 resistors). This will move the 100MHz reference clock from PLLS to PLLF

** these capacitors/resistors have shared pads as shown in the picture below

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Each SERDES block has 8 SERDESes that can be configured by protocol number.

Noticve: The Default clock assembly limits the amount of configurations according to the table below:

AB Header