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Date | Owner | Revision | Notes | ||||||||
| Noam Weidenfeld | 1.0 | Initial release | ||||||||
| Yazan Shhady | 1.1 | Add Power Consumption Measurement | ||||||||
Table of Contents |
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Low power and compact size (47x30mm).
4 x Cortex A53 @ 1.3GHz ; 12 kDMIPS.
2 x Cortex M4, 200MHz.
Powerful Neural Network up to 20 TOPS.
High quality multiple sensors ISP pipeline 2 x MIPI-CSI2 4 lanes.
Dual Camera 12MP ISP with HDR H.265/4 Video.
Best AI performance at a standard camera power consumption and cost.
Up to 8Gbytes LPDDR4 (Default 4GB)
Up to 256Gbytes eMMC (Default 32GB64GB)
Bootable 32Mbit QSPI.
A single Gigabit Ethernet interface.
Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata's certified module (Cypress chipset)
On board MIPI-CSI interface supporting Leopard camera's modules.
Industrial temperature grade
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The voltage on VBUS is 5V.
There are decupling capacitors on the SOM.
PCIe
TBD
MIPI CSI
MIPI CSI interface 1 is available on the BtB connector (See MIPI CSI-2 SOM’s Camera Interface).
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The Hailo 15 SOM supports a single dual channel I2S controller.
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The Audio main features are:
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Connector’s Signal Description
J5001
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J7
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J9
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Power & Reset
Power Architecture
The Hailo 15’s power is a single 5V source. It uses Discreet power converters to generate its power rails. The following figure describes the power architecture and power up sequencing.
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The power architecture main features are:
Single 5V power source.
1.8V output up to 1A (Need to calculate system and SOM power).
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Power Consumption
The Hilo 15 power is monitored by a voltage supervisor.
A reset can be triggered by an external reset signal (Switch) or the internal power fail. There is a pull-up on the SOM.
Resetting the SOM doesn’t turn the power rails off including the 1.8V out.
Hailo 15 Integration Manual
Power Up Sequence
The Hailo 15 is sourced by a single 5V input. All power sequences are supported on the SOM.
When using the SOM 1.8V output there is no need to consider its power sequence. If an external power source is used for the 1.8V, it needs to be power according to the power sequence rules.
Booting Options
The Hailo 15 support boot from a FLASH (QSPI) memory or from UART IF (UART1).
The Hailo 15 has one bootstrap pin, which select the boot-up interface of the M4 MCU.
The bootstrap pin, H_I2S_SDO, is being sampled with NRESET and should remain stable during the reset process.
The signal H_I2S_SDO is available on J5001-3 as a bootstrap pin and on J7-53 as an audio interface. However, one can use only one of the signal locations.
To check the boot sequencing please refer to the Hailo 15 datasheet.
I2C Interfaces
The Hailo 15 uses I2C0 interface for its internal configurations.
I2C0 is available only on the SOM.
GPIO Interfaces
The Hailo 15 uses some GPIO signals for its internal controls. Some of the signals are of the CPU and others are of the IO Expender. The following table describes the GPIO allocation.
Hailo 15 SOM Power Table:
Test Condition | Voltage | Current | Power | Tj [°C] | Tj [°C] |
|---|---|---|---|---|---|
Idle, Linux up | 5V | 520mA | 2.6W | 64°C | 53°C |
Linux up, Ethernet connected and sending packets by iperf3 | 5V | 620mA | 3.1W | 65°C | 54°C |
Linux up, wifi connected to 2.4GHz and sending packets by iperf3 | 5V | 660mA | 3.3W | 65°C | 54°C |
Linux up, wifi connected to 5GHz and sending packets by iperf3 | 5V | 740mA | 3.7W | 66°C | 55°C |
Linux up, CPU stress to maximum (4 x CPU 100%) | 5V | 700mA | 3.5W | 84°C | 59°C |
Linux up, AI stress Ultra-Performance [*] | 5V | 1.18A | 5.9W | 85°C | 60°C |
All utilities are active in the same time (Wifi, AI stress, CPU stress, Ethernet)[stress running for 1 minute] | 5V | 1.52A | 7.6W | 98°C | 72°C |
All utilities are active in the same time (Wifi, AI stress, CPU stress, Ethernet)[stress running for 3 minutes] | 5V | 1.56A | 7.8W | 116°C | 82°C |
Power and thermal tests were conducted at room temperature.
[*] AI Stress by running hailortcli run apps/detection/resources/yolov5m_wo_spp_60p_nv12_640.hef --power-mode ultra_performance
Reset
The Hilo 15 power is monitored by a voltage supervisor.
A reset can be triggered by an external reset signal (Switch) or the internal power fail. There is a pull-up on the SOM.
Resetting the SOM doesn’t turn the power rails off including the 1.8V out.
Hailo 15 Integration Manual
Power Up Sequence
The Hailo 15 is sourced by a single 5V input. All power sequences are supported on the SOM.
When using the SOM 1.8V output there is no need to consider its power sequence. If an external power source is used for the 1.8V, it needs to be power according to the power sequence rules.
Booting Options
The Hailo 15 support boot from a FLASH (QSPI) memory or from UART IF (UART1).
The Hailo 15 has one bootstrap pin, which select the boot-up interface of the M4 MCU.
The bootstrap pin, H_I2S_SDO, is being sampled with NRESET and should remain stable during the reset process.
The signal H_I2S_SDO is available on J5001-3 as a bootstrap pin and on J7-53 as an audio interface. However, one can use only one of the signal locations.
To check the boot sequencing please refer to the Hailo 15 datasheet.
I2C Interfaces
The Hailo 15 uses I2C0 interface for its internal configurations.
The Hailo 15 uses I2C0 interface for its internal configurations.
Ref. | Chip | I2C Port | Address A | Port | Description | |||||||
U5 | IO EXPANDER | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | RW | 74H | Enable parts on the SOM |
U12 | EEPROM | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | RW | 50H | SOM ID |
U6 | PCIe CLK GEN. | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | RW | 48H | PCIe clock generator |
U16 | 0P8V Core PWR | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | RW | 40H | Buck control |
J2 | Leopard Camera | 0 | Check camera datasheet. | |||||||||
I2C0 is available only on the SOM.
GPIO Interfaces
The Hailo 15 uses some GPIO signals for its internal controls. Some of the signals are of the CPU and others are of the IO Expender. The following table describes the GPIO allocation.
Signal | I/O | Description | Remarks |
H_GPIO_6 | H_GPIO_6 | Reset the IO Expander | Active Low |
H_GPIO_8 | H_GPIO_8 | IO Expander interrupt | Active Low |
WL_REG_ON | IO_EXP 0-1 | Enable the WIFI radio | Active High |
BT_REG_ON | IO_EXP 0-2 | Enable the BT radio | Active High |
ETH_RST# | IO_EXP 0-3 | Reset the Ethernet PHY | Active Low |
ENET_nINT | IO_EXP 0-4 | Ethernet PHY interrupt | Active Low |
QSPI_SEL | IO_EXP 0-4] | Select the QSPI interface | “0” FLASH memory “1” Board to Board conn. |
Hailo 15 SOM Debugging Capability
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Hailo 15 Typical Power Consumption
TBD
Hailo 15 SOM Mechanical Description
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Federal Communications Commission (FCC) Statement
TBD