Content Comparison

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Revision and Notes

Date	Owner	Revision	Notes

April

26 Apr 2020

Alon Rotman

1.0

Pre-released information
Relevant for PCB revision 1.0

October

10 Oct 2020

Alon Rotman

1.1

Update CN913x configurations
Update Connector A/B C/D pinout
Relevant for PCB rev1.1

October

29 Oct 2020

Alon Rotman

1.2

Updated CP[2:0] MPPs tables according to PCB rev1.1

Table of Contents

minLevel	1
maxLevel	7

Info

Disclaimer

No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

...

Note that all PCIe lanes specified in the CN9132 default configuration are connected to PCIe pins in the COM Express connector and are routed as 90 ohm differential pairs

CP[2:0] Multi Purpose Pins

CP0 MPP[62:0]

MPP #	Pin #	Pin Description	Notes
AP_MPP[0]	AP10	EMMC_CLK	1.8V, serial 22ohm resistor
AP_MPP[1]	AT10	EMMC_CMD	1.8V, 10K PU
AP_MPP[2]	AP16	EMMC_D0	1.8V, 10K PU
AP_MPP[3]	AP18	EMMC_D1	1.8V, 10K PU
AP_MPP[4]	AT16	EMMC_D2	1.8V, 10K PU
AP_MPP[5]	AP14	EMMC_D3	1.8V, 10K PU
AP_MPP[6]	AP12	EMMC_DS	RCLK, 10K PD
AP_MPP[7]	AT14	EMMC_D4	1.8V, 10K PU
AP_MPP[8]	AT12	EMMC_D5	1.8V, 10K PU
AP_MPP[9]	AT18	EMMC_D6	1.8V, 10K PU
AP_MPP[10]	AV18	EMMC_D7	1.8V, 10K PU
AP_MPP[11]	AY18	UART_AP_TX	PD - Reset strap 3.3V thorough level shifter
AP_MPP[12]	BA17	EMMC_RST	1.8V, 10K PD
AP_MPP[19]	AW17	UART_AP_RX	3.3V thorough level shiffter
MPP[0]	AY38	RGMII_RXD3
MPP[1]	AV38	RGMII_RXD2
MPP[2]	AW39	RGMII_RXD1
MPP[3]	AY40	RGMII_RXD0
MPP[4]	AW41	RGMII_RXCTL
MPP[5]	BA39	RGMII_RXCLK
MPP[6]	AW35	RGMII_TXD3
MPP[7]	AY36	RGMII_TXD2
MPP[8]	BA37	RGMII_TXD1
MPP[9]	AW37	RGMII_TXD0
MPP[10]	BA35	RGMII_TXCTL
MPP[11]	AV36	RGMII_TXCLK
MPP[12]	AV32	SPI1_CP0_CS1_N
MPP[13]	AY34	SPI1_CP0_MISO
MPP[14]	AT36	SPI1_CP0_CS0_N
MPP[15]	AT32	SPI1_CP0_MOSI	CPU Subsystem Clock CP0_SYS_PLL_SEL0
MPP[16]	AV34	SPI1_CP0_CLK	CPU Subsystem Clock CP0_SYS_PLL_SEL1
MPP[17]	BA29	CP0_SYS_PLL_SEL2	CPU Subsystem Clock CP0_SYS_PLL_SEL2
MPP[18]	AW29	CP0_BOOT_MODE_SEL0	CPU Subsystem Clock Options[2]
MPP[19]	AV30	CP0_BOOT_MODE_SEL1	Boot mode strap
MPP[20]	BA31	CP0_BOOT_MODE_SEL2	Boot mode strap
MPP[21]	AT30	CP0_BOOT_MODE_SEL3	Boot mode strap
MPP[22]	AY30	CP0_BOOT_MODE_SEL4	Boot mode strap
MPP[23]	AP32	CP0_BOOT_MODE_SEL5 / SMB_ALERT_N	Boot mode strap
MPP[24]	AP34	SFP_INT0	3.3V, 2.2K PU
MPP[25]	AT34		Reset strap 2.2K PD
MPP[26]	AT38	FAN_TACHO	Reset strap 10K PU
MPP[27]	AW31	AP_DDR_EVENT_N	3.3V, 10K PU
MPP[28]	AY32	CP0_PTP_PULSE
MPP[29]	BA33	CP0_PTP_CLK_IN
MPP[30]	AW33	CP0_PTP_PCLK_OUT
MPP[31]	AP36	PWRBTN_N	3.3V, 2.2K PU
MPP[32]	H30	CS_STATUS	BIOS_DIS circuitry
MPP[33]	C39	BIOS_DIS_OVERRIDE	BIOS_DIS circuitry
MPP[34]	C41	SUS_5_N	3.3V, 2.2K PU
MPP[35]	F32	I2C_MASTER_SDA	3.3V, 2.2K PU used addresses: 0x53, 0x2F, 0x6A, 0x51
MPP[36]	H32	I2C_MASTER_SCL	3.3V, 2.2K PU
MPP[37]	F34	I2C0_CP0_SDA	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[38]	H34	I2C0_CP0_SCL	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[39]	F30	FAN_PWM
MPP[40]	F36	SMI_MDIO	3.3V, 2.2K PU
MPP[41]	H36	SMI_MDC	3.3V, 2.2K PU
MPP[42]	E39	XSMI_MDC	3.3V, 2.2K PU
MPP[43]	D30	XSMI_MDIO	3.3V, 2.2K PU
MPP[44]	D38		Reset strap
MPP[45]	A39		Reset strap
MPP[46]	C37	SYS_PLL_SEL3	CPU Subsystem Clock Options[3]
MPP[47]	A37		Reset strap, PD
MPP[48]	B40		Reset strap
MPP[49]	B38	CP0_VHV_EN
MPP[50]	C35	UART2_TX
MPP[51]	D34	UART2_RX
MPP[52]	A35	CP0_RCVR1_CLK	25MHz for SYNC-E
MPP[53]	B36	AP_VHV_EN
MPP[54]	D36	CP0_RCVR2_CLK	25MHz for SYNC-E connected to PHY
MPP[55]	B34	SD_CARD_DETECT_N	3.3V, 2.2K PU
MPP[56]	D32	SD_CLK	3.3V
MPP[57]	B32	SD_CMD	3.3V
MPP[58]	A33	SD_D0	3.3V
MPP[59]	C33	SD_D1	3.3V
MPP[60]	A31	SD_D2	3.3V
MPP[60]	C31	SD_D3	3.3V
MPP[62]	B30	NC

...

Pins marked with ~~strikethrough~~ are unused / unconnected pins
Pins marked with Red are GND or power

AB Header

Show 102550100110 entries

...

Notes
Driving IC
Schematics Pin Name
Pin Number
Pin Number
Schematics Pin Name
Driving IC
Notes
GND (FIXED)
A1
B1
GND (FIXED)
CP0 RGMII through 88E1512 PHY
GBE0_MDI3-
A2
B2
GBE0_ACT#
88E1512 PHY LED[1]
CP0 RGMII through 88E1512 PHY
GBE0_MDI3+
A3
B3
LPC_FRAME#
Not used
GBE0_LINK100#
A4
B4
LPC_AD0
88E1512 PHY LED[0]
GBE0_LINK1000#
A5
B5
LPC_AD1
CP0 RGMII through 88E1512 PHY
GBE0_MDI2-
A6
B6
LPC_AD2
CP0 RGMII through 88E1512 PHY
GBE0_MDI2+
A7
B7
LPC_AD3
88E1512 PHY LED[2]
GBE0_LINK#
A8
B8
LPC_DRQ0#
CP0 RGMII through 88E1512 PHY
GBE0_MDI1-
A9
B9
LPC_DRQ1#
CP0 RGMII through 88E1512 PHY
GBE0_MDI1+
A10
B10
LPC_CLK
GND (FIXED)
A11
B11
GND (FIXED)
CP0 RGMII through 88E1512 PHY
GBE0_MDI0-
A12
B12
PWRBTN#
CP0 MPP[31]
3.3V, 2.2k pull-up
CP0 RGMII through 88E1512 PHY
GBE0_MDI0+
A13
B13
SMB_CK
CP0 MPP[36] through
PCA9547APW
3.3V, 2.2k pull-up
Not used
GBE0_CTREF
A14
B14
SMB_DAT
CP0 MPP[35] through
PCA9547APW
3.3V, 2.2k pull-up
Not used
SUS_S3#
A15
B15
SMB_ALERT#
CP0 MPP[23]
3.3V, 2.2k pull-up
Serial 10nF
CP1 SD[3]
SATA0_TX+
A16
B16
SATA1_TX+
CP2 SD[3]
Serial 10nF
Serial 10nF
CP1 SD[3]
SATA0_TX-
A17
B17
SATA1_TX-
CP2 SD[3]
Serial 10nF
Not used
SUS_S4#
A18
B18
SUS_STAT#
Serial 10nF
CP1 SD[3]
SATA0_RX+
A19
B19
SATA1_RX+
CP2 SD[3]
Serial 10nF
Serial 10nF
CP1 SD[3]
SATA0_RX-
A20
B20
SATA1_RX-
CP2 SD[3]
Serial 10nF
GND (FIXED)
A21
B21
GND (FIXED)
Not used
PCIE_TX15+
A22
B22
PCIE_RX15+
Not used
PCIE_TX15-
A23
B23
PCIE_RX15-
3.3v, 2.2k pull-up
CP0 MPP[34]
SUS_S5#
A24
B24
PWR_OK
Power enable
3.3V, 4.7K pull-up
Refer to power-up sequence
Not used
PCIE_TX14+
A25
B25
PCIE_RX14+
Not used
PCIE_TX14-
A26
B26
PCIE_RX14+
3.3V
CP1 MPP[11]
BATLOW#
A27
B27
WDT
3.3V
CP1 MPP[39]
SATA_ACT#
A28
B28
RSVD
CP2 MPP[8]
RSVD[8]
1.8V / 3.3V
RSVD[0]
1.8V / 3.3V
CP2 MPP[0]
RSVD
A29
B29
RSVD
CP2 MPP[9]
RSVD[9]
1.8V / 3.3V
RSVD[1]
1.8V / 3.3V
CP2 MPP[1]
RSVD
A30
B30
RSVD
CP2 MPP[10]
RSVD[10]
1.8V / 3.3V
GND (FIXED)
A31
B31
GND (FIXED)
RSVD[2]
1.8V / 3.3V
CP2 MPP[2]
RSVD
A32
B32
SPKR
CP1 MPP[12]
3.3V
RSVD[3]
1.8V / 3.3V
CP2 MPP[3]
RSVD
A33
B33
I2C_CK
CP0 MPP[36]
SPD on address 0x53
3.3v, 2.2k pull-up
SPI CS0/1 switch
BIOS_DIS0#
A34
B34
I2C_DAT
CP0 MPP[35]
SPD on address 0x53
3.3V
CP1 MPP[33]
THRMTRIP#
A35
B35
THRM#
CP1 MPP[34]
Not used
PCIE_TX13+
A36
B36
PCIE_RX13+
Not used
PCIE_TX13-
A37
B37
PCIE_RX13-
GND
A38
B38
GND
Serial 220nF
CP1 SD[4]
PCIE_TX12+
A39
B39
PCIE_RX12+
CP1 SD[4]
Serial 220nF
CP1 SD[4]
PCIE_TX12-
A40
B40
PCIE_RX12+
CP1 SD[4]
GND (FIXED)
A41
B41
GND (FIXED)
CP1 USB2[0]
USB2-
A42
B42
USB3-
CP0 USB2[1]
CP1 USB2[0]
USB2+
A43
B43
USB3+
CP0 USB2[1]
USB_2_3_OC#
A44
B44
USB_0_1_OC#
CP0 USB2[0]
USB0-
A45
B45
USB1-
CP2 USB2[0]
CP0 USB2[0]
USB0+
A46
B46
USB1+
CP2 USB2[0]
3.3V, 1uF, diode sharing with 3.3V
Not in use by default
VCC_RTC
A47
B47
ESPI_EN
RSVD[4]
1.8V / 3.3V
CP2 MPP[4]
RSVD
A48
B48
RSVD
CP2 MPP[11]
RSVD[11]
1.8V / 3.3V
CP1 MPP[29]
RSVD / PTP_CLK_IN1
A49
B49
SYS_RESET#
System Reset input
3.3V, 2.2k pull-up
LPC_SERIRQ
A50
B50
CB_RESET#
Carrier board reset output, can be used as PERST
3.3V, full drive
GND (FIXED)
A51
B51
GND (FIXED)
Serial 220nF
CP1 SD[1]
PCIE_TX5+
A52
B52
PCIE_RX5+
CP1 SD[0]
Serial 220nF
CP1 SD[1]
PCIE_TX5-
A53
B53
PCIE_RX5-
CP1 SD[0]
microSD D[0]
CP0 MPP[58]
GPI0 / SDIO_SD0
A54
B54
GPO1 / SDIO_CMD
CP0 MPP[57]
microSD CMD
Serial 220nF
CP1 SD[0]
PCIE_TX4+
A55
B55
PCIE_RX4+
CP1 SD[0]
Serial 220nF
CP1 SD[0]
PCIE_TX4-
A56
B56
PCIE_RX4-
CP1 SD[0]
GND
A57
B57
GPO2
CP2 MPP[40]
3.3V, 2.2k pull-up
Serial 220nF
CP0 SD[3]
PCIE_TX3+
A58
B58
PCIE_RX3+
CP0 SD[3]
Serial 220nF
CP0 SD[3]
PCIE_TX3-
A59
B59
PCIE_RX3-
CP0 SD[3]
GND (FIXED)
A60
B60
GND (FIXED)
Serial 220nF
CP0 SD[2]
PCIE_TX2+
A61
B61
PCIE_RX2+
CP0 SD[2]
Serial 220nF
CP0 SD[2]
PCIE_TX2-
A62
B62
PCIE_RX2-
CP0 SD[2]
microSD D[1]
CP0 MPP[59]
GPI1 / SDIO_SD1
A63
B63
GPO3 / SD_CD
CP0 MPP[55]
micro SD CD
Serial 220nF
CP0 SD[1]
PCIE_TX1+
A64
B64
PCIE_RX1+
CP0 SD[1]
Serial 220nF
CP0 SD[1]
PCIE_TX1-
A65
B65
PCIE_RX1-
CP0 SD[1]
GND
A66
B66
WAKE0#
CP1 MPP[40]
microSD D[2]
CP0 MPP[60]
GPI2 / SDIO_SD2
A67
B67
WAKE1#
CP1 MPP[51]
Serial 220nF
CP0 SD[0]
PCIE_TX0+
A68
B68
PCIE_RX0+
CP0 SD[0]
Serial 220nF
CP0 SD[0]
PCIE_TX0-
A69
B69
PCIE_RX0-
CP0 SD[0]
GND (FIXED)
A70
B70
GND (FIXED)
Serial 220nF
CP0 SD[5]
PCIE_TX8+
A71
B71
PCIE_RX8+
CP0 SD[5]
Serial 220nF
CP0 SD[5]
PCIE_TX8-
A72
B72
PCIE_RX8-
CP0 SD[5]
GND
A73
B73
GND
PCIE_TX9+
A74
B74
PCIE_RX9+
PCIE_TX9-
A75
B75
PCIE_RX9-
GND
A76
B76
GND
PCIE_TX10+
A77
B77
PCIE_RX10+
PCIE_TX10-
A78
B78
PCIE_RX10-
GND
A79
B79
GND
GND (FIXED)
A80
B80
GND (FIXED)
PCIE_TX11+
A81
B81
PCIE_RX11+
PCIE_TX11-
A82
B82
PCIE_RX11-
GND
A83
B83
GND
NCSI_TX_EN
A84
B84
VCC_5V_SBY
microSD D[3]
CP0 MPP[61]
GPI3 / SDIO_SD3
A85
B85
VCC_5V_SBY
RSVD[5]
1.8V / 3.3V
CP2 MPP[5]
RSVD
A86
B86
VCC_5V_SBY
RSVD[7]
1.8V / 3.3V
CP2 MPP[7]
RSVD
A87
B87
VCC_5V_SBY
HCSL PCIe Gen3 compliant
100MHz clock output
PCIE_CK_REF+
A88
B88
BIOS_DIS1#
HCSL PCIe Gen3 compliant
100MHz clock output
PCIE_CK_REF-
A89
B89
NCSI_RX_ER
GND (FIXED)
A90
B90
GND (FIXED)
3.3v power. Gated by 12v input
SPI_POWER
A91
B91
NCSI_CLK_IN
3.3V SPI MISO
CP0 MPP[13]
SPI_MISO
A92
B92
NCSI_RXD1
microSD CLK
CP0 MPP[56]
GPO0 / SDIO_CLK
A93
B93
NCSI_RXD0
3.3V SPI CLK
CP0 MPP[16]
SPI_CLK
A94
B94
NCSI_CRS_DV
3.3V SPI MOSI
CP0 MPP[15]
SPI_MOSI
A95
B95
NCSI_TXD1
3.3V
SLB9670
Not assembled by default
TPM_PP
A96
B96
NCSI_TXD0
TYPE10#
A97
B97
SPI_CS#
3.3V SPI CS#
3.3V
AP MPP[11]
SER0_TX
A98
B98
NCSI_ARB_IN
3.3V
AP MPP[19]
SER0_RX
A99
B99
NCSI_ARB_OUT
GND (FIXED)
A100
B100
GND (FIXED)
3.3V
CP0 MPP[50]
CAN0/SER1_TX
A101
B101
FAN_PWMOUT
CP0 MPP[39] & EMC2301
3.3V
CP0 MPP[51]
CAN0/SER1_RX
A102
B102
FAN_TACHIN
CP0 MPP[26] & EMC2301
LID#
A103
B103
SLEEP#
12v input (9v-15v)
VCC_12V
A104
B104
VCC_12V
12V input (9v-15v)
12v input (9v-15v)
VCC_12V
A105
B105
VCC_12V
12V input (9v-15v)
12v input (9v-15v)
VCC_12V
A106
B106
VCC_12V
12V input (9v-15v)
12v input (9v-15v)
VCC_12V
A107
B107
VCC_12V
12V input (9v-15v)
12v input (9v-15v)
VCC_12V
A108
B108
VCC_12V
12V input (9v-15v)
12v input (9v-15v)
VCC_12V
A109
B109
VCC_12V
12V input (9v-15v)
GND (FIXED)
A110
B110
GND (FIXED)
...

Version	Old Version 3	New Version 4
Changes made by	SolidRun	SolidRun
Saved on	Nov 08, 2021	Nov 08, 2021

Versions Compared

Key

Revision and Notes

CP[2:0] Multi Purpose Pins

CP0 MPP[62:0]

AB Header

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
		GND (FIXED)	A1	B1	GND (FIXED)
	CP0 RGMII through 88E1512 PHY	GBE0_MDI3-	A2	B2	GBE0_ACT#	88E1512 PHY LED[1]
	CP0 RGMII through 88E1512 PHY	GBE0_MDI3+	A3	B3	~~LPC_FRAME#~~
Not used		~~GBE0_LINK100#~~	A4	B4	~~LPC_AD0~~
	88E1512 PHY LED[0]	GBE0_LINK1000#	A5	B5	~~LPC_AD1~~
	CP0 RGMII through 88E1512 PHY	GBE0_MDI2-	A6	B6	~~LPC_AD2~~
	CP0 RGMII through 88E1512 PHY	GBE0_MDI2+	A7	B7	~~LPC_AD3~~
	88E1512 PHY LED[2]	GBE0_LINK#	A8	B8	~~LPC_DRQ0#~~
	CP0 RGMII through 88E1512 PHY	GBE0_MDI1-	A9	B9	~~LPC_DRQ1#~~
	CP0 RGMII through 88E1512 PHY	GBE0_MDI1+	A10	B10	~~LPC_CLK~~
		GND (FIXED)	A11	B11	GND (FIXED)
	CP0 RGMII through 88E1512 PHY	GBE0_MDI0-	A12	B12	PWRBTN#	CP0 MPP[31]	3.3V, 2.2k pull-up
	CP0 RGMII through 88E1512 PHY	GBE0_MDI0+	A13	B13	SMB_CK	CP0 MPP[36] through PCA9547APW	3.3V, 2.2k pull-up
Not used		~~GBE0_CTREF~~	A14	B14	SMB_DAT	CP0 MPP[35] through PCA9547APW	3.3V, 2.2k pull-up
Not used		~~SUS_S3#~~	A15	B15	SMB_ALERT#	CP0 MPP[23]	3.3V, 2.2k pull-up
Serial 10nF	CP1 SD[3]	SATA0_TX+	A16	B16	SATA1_TX+	CP2 SD[3]	Serial 10nF
Serial 10nF	CP1 SD[3]	SATA0_TX-	A17	B17	SATA1_TX-	CP2 SD[3]	Serial 10nF
Not used		~~SUS_S4#~~	A18	B18	~~SUS_STAT#~~
Serial 10nF	CP1 SD[3]	SATA0_RX+	A19	B19	SATA1_RX+	CP2 SD[3]	Serial 10nF
Serial 10nF	CP1 SD[3]	SATA0_RX-	A20	B20	SATA1_RX-	CP2 SD[3]	Serial 10nF
		GND (FIXED)	A21	B21	GND (FIXED)
Not used		~~PCIE_TX15+~~	A22	B22	~~PCIE_RX15+~~
Not used		~~PCIE_TX15-~~	A23	B23	~~PCIE_RX15-~~
3.3v, 2.2k pull-up	CP0 MPP[34]	SUS_S5#	A24	B24	PWR_OK	Power enable	3.3V, 4.7K pull-up Refer to power-up sequence
Not used		~~PCIE_TX14+~~	A25	B25	~~PCIE_RX14+~~
Not used		~~PCIE_TX14-~~	A26	B26	~~PCIE_RX14+~~
3.3V	CP1 MPP[11]	BATLOW#	A27	B27	~~WDT~~
3.3V	CP1 MPP[39]	SATA_ACT#	A28	B28	RSVD	CP2 MPP[8]	RSVD[8] 1.8V / 3.3V
RSVD[0] 1.8V / 3.3V	CP2 MPP[0]	RSVD	A29	B29	RSVD	CP2 MPP[9]	RSVD[9] 1.8V / 3.3V
RSVD[1] 1.8V / 3.3V	CP2 MPP[1]	RSVD	A30	B30	RSVD	CP2 MPP[10]	RSVD[10] 1.8V / 3.3V
		GND (FIXED)	A31	B31	GND (FIXED)
RSVD[2] 1.8V / 3.3V	CP2 MPP[2]	RSVD	A32	B32	SPKR	CP1 MPP[12]	3.3V
RSVD[3] 1.8V / 3.3V	CP2 MPP[3]	RSVD	A33	B33	I2C_CK	CP0 MPP[36]	SPD on address 0x53
3.3v, 2.2k pull-up	SPI CS0/1 switch	BIOS_DIS0#	A34	B34	I2C_DAT	CP0 MPP[35]	SPD on address 0x53
3.3V	CP1 MPP[33]	THRMTRIP#	A35	B35	THRM#	CP1 MPP[34]
Not used		~~PCIE_TX13+~~	A36	B36	~~PCIE_RX13+~~
Not used		~~PCIE_TX13-~~	A37	B37	~~PCIE_RX13-~~
		GND	A38	B38	GND
Serial 220nF	CP1 SD[4]	PCIE_TX12+	A39	B39	PCIE_RX12+	CP1 SD[4]
Serial 220nF	CP1 SD[4]	PCIE_TX12-	A40	B40	PCIE_RX12+	CP1 SD[4]
		GND (FIXED)	A41	B41	GND (FIXED)
	CP1 USB2[0]	USB2-	A42	B42	USB3-	CP0 USB2[1]
	CP1 USB2[0]	USB2+	A43	B43	USB3+	CP0 USB2[1]
		~~USB_2_3_OC#~~	A44	B44	~~USB_0_1_OC#~~
	CP0 USB2[0]	USB0-	A45	B45	USB1-	CP2 USB2[0]
	CP0 USB2[0]	USB0+	A46	B46	USB1+	CP2 USB2[0]
3.3V, 1uF, diode sharing with 3.3V Not in use by default		VCC_RTC	A47	B47	~~ESPI_EN~~
RSVD[4] 1.8V / 3.3V	CP2 MPP[4]	RSVD	A48	B48	RSVD	CP2 MPP[11]	RSVD[11] 1.8V / 3.3V
	CP1 MPP[29]	RSVD / PTP_CLK_IN1	A49	B49	SYS_RESET#	System Reset input	3.3V, 2.2k pull-up
		~~LPC_SERIRQ~~	A50	B50	CB_RESET#	Carrier board reset output, can be used as PERST	3.3V, full drive
		GND (FIXED)	A51	B51	GND (FIXED)
Serial 220nF	CP1 SD[1]	PCIE_TX5+	A52	B52	PCIE_RX5+	CP1 SD[0]
Serial 220nF	CP1 SD[1]	PCIE_TX5-	A53	B53	PCIE_RX5-	CP1 SD[0]
microSD D[0]	CP0 MPP[58]	GPI0 / SDIO_SD0	A54	B54	GPO1 / SDIO_CMD	CP0 MPP[57]	microSD CMD
Serial 220nF	CP1 SD[0]	PCIE_TX4+	A55	B55	PCIE_RX4+	CP1 SD[0]
Serial 220nF	CP1 SD[0]	PCIE_TX4-	A56	B56	PCIE_RX4-	CP1 SD[0]
		GND	A57	B57	GPO2	CP2 MPP[40]	3.3V, 2.2k pull-up
Serial 220nF	CP0 SD[3]	PCIE_TX3+	A58	B58	PCIE_RX3+	CP0 SD[3]
Serial 220nF	CP0 SD[3]	PCIE_TX3-	A59	B59	PCIE_RX3-	CP0 SD[3]
		GND (FIXED)	A60	B60	GND (FIXED)
Serial 220nF	CP0 SD[2]	PCIE_TX2+	A61	B61	PCIE_RX2+	CP0 SD[2]
Serial 220nF	CP0 SD[2]	PCIE_TX2-	A62	B62	PCIE_RX2-	CP0 SD[2]
microSD D[1]	CP0 MPP[59]	GPI1 / SDIO_SD1	A63	B63	GPO3 / SD_CD	CP0 MPP[55]	micro SD CD
Serial 220nF	CP0 SD[1]	PCIE_TX1+	A64	B64	PCIE_RX1+	CP0 SD[1]
Serial 220nF	CP0 SD[1]	PCIE_TX1-	A65	B65	PCIE_RX1-	CP0 SD[1]
		GND	A66	B66	WAKE0#	CP1 MPP[40]
microSD D[2]	CP0 MPP[60]	GPI2 / SDIO_SD2	A67	B67	WAKE1#	CP1 MPP[51]
Serial 220nF	CP0 SD[0]	PCIE_TX0+	A68	B68	PCIE_RX0+	CP0 SD[0]
Serial 220nF	CP0 SD[0]	PCIE_TX0-	A69	B69	PCIE_RX0-	CP0 SD[0]
		GND (FIXED)	A70	B70	GND (FIXED)
Serial 220nF	CP0 SD[5]	PCIE_TX8+	A71	B71	PCIE_RX8+	CP0 SD[5]
Serial 220nF	CP0 SD[5]	PCIE_TX8-	A72	B72	PCIE_RX8-	CP0 SD[5]
		GND	A73	B73	GND
		~~PCIE_TX9+~~	A74	B74	~~PCIE_RX9+~~
		~~PCIE_TX9-~~	A75	B75	~~PCIE_RX9-~~
		GND	A76	B76	GND
		~~PCIE_TX10+~~	A77	B77	~~PCIE_RX10+~~
		~~PCIE_TX10-~~	A78	B78	~~PCIE_RX10-~~
		GND	A79	B79	GND
		GND (FIXED)	A80	B80	GND (FIXED)
		~~PCIE_TX11+~~	A81	B81	~~PCIE_RX11+~~
		~~PCIE_TX11-~~	A82	B82	~~PCIE_RX11-~~
		GND	A83	B83	GND
		~~NCSI_TX_EN~~	A84	B84	~~VCC_5V_SBY~~
microSD D[3]	CP0 MPP[61]	GPI3 / SDIO_SD3	A85	B85	~~VCC_5V_SBY~~
RSVD[5] 1.8V / 3.3V	CP2 MPP[5]	RSVD	A86	B86	~~VCC_5V_SBY~~
RSVD[7] 1.8V / 3.3V	CP2 MPP[7]	RSVD	A87	B87	~~VCC_5V_SBY~~
HCSL PCIe Gen3 compliant	100MHz clock output	PCIE_CK_REF+	A88	B88	~~BIOS_DIS1#~~
HCSL PCIe Gen3 compliant	100MHz clock output	PCIE_CK_REF-	A89	B89	~~NCSI_RX_ER~~
		GND (FIXED)	A90	B90	GND (FIXED)
	3.3v power. Gated by 12v input	SPI_POWER	A91	B91	~~NCSI_CLK_IN~~
3.3V SPI MISO	CP0 MPP[13]	SPI_MISO	A92	B92	~~NCSI_RXD1~~
microSD CLK	CP0 MPP[56]	GPO0 / SDIO_CLK	A93	B93	~~NCSI_RXD0~~
3.3V SPI CLK	CP0 MPP[16]	SPI_CLK	A94	B94	~~NCSI_CRS_DV~~
3.3V SPI MOSI	CP0 MPP[15]	SPI_MOSI	A95	B95	~~NCSI_TXD1~~
3.3V	SLB9670 Not assembled by default	TPM_PP	A96	B96	~~NCSI_TXD0~~
		~~TYPE10#~~	A97	B97	SPI_CS#	3.3V SPI CS#
3.3V	AP MPP[11]	SER0_TX	A98	B98	~~NCSI_ARB_IN~~
3.3V	AP MPP[19]	SER0_RX	A99	B99	~~NCSI_ARB_OUT~~
		GND (FIXED)	A100	B100	GND (FIXED)
3.3V	CP0 MPP[50]	CAN0/SER1_TX	A101	B101	FAN_PWMOUT	CP0 MPP[39] & EMC2301
3.3V	CP0 MPP[51]	CAN0/SER1_RX	A102	B102	FAN_TACHIN	CP0 MPP[26] & EMC2301
		~~LID#~~	A103	B103	~~SLEEP#~~
	12v input (9v-15v)	VCC_12V	A104	B104	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A105	B105	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A106	B106	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A107	B107	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A108	B108	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A109	B109	VCC_12V	12V input (9v-15v)
		GND (FIXED)	A110	B110	GND (FIXED)